(1) Field of the Invention
This invention relates to a memory type semiconductor device and in particular, to an improved process for forming closely spaced, buried conductive bit and code implant regions for ROM devices.
(2) Description of the Prior Art
To achieve microminiaturization of integrated circuit devices, individual elements have been made very small and the elements have been closely packed. As read only memory devices (i.e. ROM's) are scaled down in dimensions, there is a continuous challenge to maintain close spacings between the buried bit lines to obtain higher density cell structures. Also, the spacing between the bit lines and code implant areas is critical to maintaining consistent bit line resistances which is a important factor to ROM read speed. Code implants and bit lines are composed of an opposite type impurities (e.g., N+ bit lines and P+ code implants). A large bit line resistance due to a code impurity overlap will degrade the data reading speed. A conventional method to protect N+ buried lines from code impurity overlaps, is to use the metal lines as an implant mask. However, metal line pitches are normally larger than N+ line pitches. This is because the metal line photolithography and etching processes are not as precise as the photolithography and ion implant processes used to form buried N+ bit lines. As a result, the conventional method to protect the N+ buried line uses one metal line as a implant block for every other N+ buried bit line. It is not possible to use one metal line to cover each buried N+ line because the metal lines pitches are larger than the N+ buried line pitches. Because the conventional process uses metal lines as a code mask for only half the bit lines, the bit lines not protected by metal lines are often exposed to code implants which raises the bit line resistance thereby reducing the reading speed.
In the prior art process, as shown in FIGS. 1 and 2, buried N+ lines 11, 13 are implanted into substrate 10 using conventional implant processes. Next, thin insulating layer 12 is deposited on the substrate 10 surface. Then polysilicon word line 14 is deposited over oxide 12. Following this, glass layer 16 is deposited over polysilicon word lines 14 and insulating layer 12. Metal layer 18 is deposited over glass layer 16. Conventional photolithography processes are used to form photoresist lines 20 on the metal layer 18 and to form metal lines 22 shown in FIG. 2. The metal lines 22 are formed over every other bit line 11, leaving alternate bit lines 13 uncovered. It is not possible to place metal lines over every bit line because the minimum line pitch is larger for metal lines than for the bit lines. Line pitch is the distance between the one side of a line and the same side of an adjacent line. This is shown in FIG. 1, where pitch 24 illustrates the pitch of the buried bit lines and pitch 26 illustrates the pitch of the metal lines. Metal line pitch 26 is larger than bit line pitch 24 because of the larger inherent photolithography and etching imprecision in the metal process compared to the bit line implant and photolithography processes. Moreover, the metal etching process is not as precise as the bit line implantation process. Also, because of the uneven surface topology and other factors, the metal photolithography process is not as accurate as the bit line photolithography process.
Next, a photoresist layer is applied over the metal lines 22 and the glass layer 16. Using conventional photolithographic processes, opening are formed in the photoresist layer in areas where the code implants are desired. The remaining photoresist 23 is used as a code implant mask. When the bit lines are N+ type regions, a boron ion is normally used for the code implant. Next, the surface is implanted with boron forming code implant regions 28, 29 as shown in FIG. 2 and FIG. 2A. It should be noted that the metal lines 22 over the bit lines 11 act as a mask for the code implant therefore preventing overlap of the code implant and bit lines. Any overlap of boron code implant regions 28, 29 with the N-type bit lines 13 will increase the resistance of the bit line because of the compensation effect of p-type and n-type impurity mixing. Since in the conventional process only one half of the bit lines 11 are protected from code implant by a metal line, the bit lines 13 that are implanted with boron have a high resistance which reduces reading speed.
As shown in FIG. 2 and FIG. 2A, using the conventional process, when code implants 28 are required for two adjacent cells, the code implant overlaps the center bit line 13 thereby increasing bit line resistance and reducing the read speed. A memory cell is comprised of two adjacent bit lines and the channel region between the lines. As shown in FIG. 2 code implant 28, formed through opening 27, necessarily must overlap the bit line 13 since a metal is not covering bit line 13. The alternate situation is illustrated by opening 25. Code implant 29 partially overlaps bit line 13 while metal line 22 protects the adjacent bit line 11.
In addition, to reduce manufacturing costs, the processes utilized to achieve the bit and code patterns must be relatively simple, repeatable and use a minimum number to manufacturing steps.